Search Results

Background Rail programs operate under strict RAMS and functional-safety requirements. Standards such as EN 50126 and EN 50129 drive disciplined evidence: reliability prediction, availability/maintainability planning, and quantitative safety demonstrations. Company Overview A prominent engineering company leading a rail line project including rail signaling, stations power, IT, PA, CCTV, AFC, fire detection and more... Challenges The company needs to provide: RAM Analysis:  Perform detailed analysis to minimize service affecting failures and comply with availability requirements. Safety Analysis:  Identify hazards, single points of failure, and calculate probability of severe safety events. Compliance:  Achieve and demonstrate compliance with rigorous rail safety standards (EN 50126/50128/50129). Solution Implementation RAM Analysis:  Detailed System level RAM analysis was conducted using BQR software: fiXtress® for MTBF prediction. FMEA / FMECA and Diagnostics Analysis for identification of service affecting events and their detection and mitigation. RBD for MTBCF, MTTR and Availability calculations accounting for redundancies. apmOptimizer® for spare parts optimization related to system availability and no shortage probability. Safety Analysis:  Safety analysis was conducted using: FMEA / FMECA and Diagnostics Analysis for identification of safety related failure modes, their detection and mitigation FTA for probability calculation of safety events, and finding the minimal number of events that lead to them. Results Using BQR software for the analyses, the company was able to: Conduct detailed and efficient RAMS analysis , achieve compliance with the customer requirements as well as with EN 50126 and EN 50129 standards. Save money by using the recommended spare parts. Reuse project data as basis for future projects. Conclusion BQR software was successfully used for RAMS analysis of a rail project, helping the company to achieve the customer and regulatory requirements. to learn how BQR solutions can streamline your RAMS and System Engineering needs.

Equipment reliability is typically measured by Mean Time Between Failure (MTBF) or failure probability vs. time, where time measures operation hours. When electronic equipment is not used, a user may switch the power off, expecting that next time the device is turned on, it will operate as before. Thus, the failure rate during non-operation is often assumed to be zero. However, in some cases, when a product is not used for a long period of time, it malfunctions when turned back on.   The main reason for the failure of electronic devices after long periods of inactivity is humidity. Electronic components are sensitive to moisture. When exposed to moisture, components develop corrosion that may in some cases result in short circuits. The moisture content in the air depends on the relative humidity with higher relative humidity meaning higher moisture content.   Humidity is an issue for outdoor and naval equipment, as well as for data centers and large storage facilities where humidity control is expensive.   Humidity causes fewer product failures during operation because the heat generated inside the device packaging decreases the relative humidity, reducing the amount of moisture.   There are common strategies to protect against humidity and moisture such as hermetic sealing of packages, use of desiccants, and dehumidifiers, or keeping equipment in warm stand-by.   BQR in collaboration with its customers developed a unique model to calculate the reliability of electronic equipment, accounting for the relative humidity during non-operation time. This model is part of fiXtress® BQR’s reliability and MTBF prediction software.

So, you invested time and effort to conduct a FMECA (Failure Mode, Effects, and Criticality Analysis) for your product/system. You identified potential failure modes, and single points of failure, evaluated the potential effects and their severity, and calculated the probability. Finally, you assigned risk to each failure mode based on a criticality matrix. Now it is time to prepare a report, but what should you include in the report? The following is also applicable for design FMEA, process FMEA, and risk priority number (RPN) analyses. Here are a few tips for writing a FMECA report: FMECA report is a technical document that should be as self-contained as possible and maintain traceability. Therefore, your report should include: A description of the analyzed product/system Document version control Scope of the analysis: which parts of the product/system are analyzed, and which are not? For example: When conducting a FMECA for a server, is the UPS part of the analysis or not? Often 3rd party equipment or GFE (Government Furnished Equipment) are excluded. References to product/system technical documents which were the basis of the analysis References to data sources such as failure rate prediction methods and databases, failure mode libraries You should also describe the analysis goals. FMECA usually focuses on safety or diagnostics and testability  but may also be used to identify financial and environmental risks. The FMECA report will probably be read by executives and reliability or safety engineers. Clear conclusions and recommendations should be provided, and in some cases also an executive summary.What are the system-level failure modes (end effects)?What is the severity of each end effect?How many failure modes fall within each cell of the risk matrix? FMECA is often conducted according to a standard e.g., MIL-STD 1629A. You should include the methodology of the FMECA and definitions of severity, criticality, and risk. Detailed FMECA tables should also be included so that the reviewing engineer will have access to the complete body of work. BQR’s software can help you to quickly conduct a FMECA, identify single points of failure, mitigate failure modes with severe effects, and generate all the tables you need for your report. Need more help? BQR also provides FMECA professional services. So, what do your FMECA project need?

In the competitive landscape of electronic design, ensuring reliability and efficiency is paramount. For companies in high-stakes industries like aerospace, defense, and medical, the tools you choose can make all the difference. That’s where fiXtress® and Synthelyzer™ come in—two cutting-edge solutions that empower engineers to streamline their design processes and enhance product reliability. Transforming Challenges into Solutions Frederic Guitard, COO of Elix Systems SA, recently shared his team’s transformative experience with fiXtress®. Prior to integrating this innovative tool, Elix Systems faced significant hurdles in calculating the Mean Time Between Failures (MTBF) for their systems. The reliance on external resources not only slowed down their workflow but also introduced potential inaccuracies. With fiXtress®, the landscape shifted dramatically. Frederic noted, “We chose it due to its integration with our existing EDA tool.” This seamless integration allowed the Elix team to perform MTBF predictions in-house, leading to increased efficiency and reduced reliance on subcontractors. The ability to insert stresses directly within the schematic design empowered their engineers to iterate more quickly and flexibly. Enhancing Reliability with Synthelyzer™ Complementing fiXtress®, the Synthelyzer™ ECAD Plugin takes reliability analysis a step further. This tool automates electrical stress analysis, component derating, and FMEA (Failure Modes and Effects Analysis), all within the familiar environment of your ECAD software. Frederic emphasized the significant time savings achieved through Synthelyzer™, stating, “It automates manual component derating, streamlining the process.” This automation not only minimizes human error but also accelerates the design cycle, allowing engineers to focus on what they do best—innovating. Moreover, Synthelyzer™ utilizes thermal simulation data to enhance derating accuracy, providing critical insights into component performance. By identifying overstressed components and offering actionable recommendations, it helps ensure that designs are robust and reliable. Key Features Driving Success Both fiXtress® and Synthelyzer™ come packed with features that address the specific needs of today’s electronic designers: Comprehensive Stress Analysis:  Both tools offer in-depth analyses of electrical stress, ensuring that components can endure operational demands. MTBF Prediction:  Realistic MTBF estimates based on actual stress data enable better planning and maintenance strategies. Extensive Component Libraries:  Access to validated components simplifies the selection process and reduces the risk of failure. Seamless Integration:  Both solutions easily integrate with popular EDA tools, allowing for in-workflow analysis that enhances productivity. Proven Impact on Project Outcomes Frederic’s experience with fiXtress® and Synthelyzer™ is a testament to their effectiveness. By eliminating the need for subcontractors for MTBF calculations, Elix Systems can now move faster through iterative design loops. The result? More reliable products that meet the stringent demands of their industry. “I would rate fiXtress® an 8 out of 10,” Frederic noted, highlighting how the tool has consistently helped the team achieve their objectives while offering a roadmap for future enhancements. Conclusion For companies striving to improve reliability and efficiency in electronic design, fiXtress® and Synthelyzer™ offer powerful, integrated solutions. By empowering teams to conduct thorough reliability analyses in-house, these tools not only save time but also enhance product quality. Are you ready to transform your design process and elevate your products to the next level? Explore fiXtre ss®  and Synthelyzer™ and join the ranks of innovative companies like Elix Systems SA that are setting new standards in reliability and performance. Your journey toward enhanced electronic design begins here!

Introduction As products and systems become increasingly complex, the risk of technical failures rises. However, it is possible to reduce the likelihood that a failure will lead to a severe accident. Lowering safety risks is essential not only for meeting customer safety requirements but also for enhancing your company's reputation. Method 1: Increase Components’ Reliability Advantages: Reduced Failure Rate:  Enhancing component reliability lowers the system failure rate, which directly decreases the probability of safety incidents. Key metrics such as Mean Time Between Failure (MTBF) and Failure Rate serve as standard measures of reliability. Disadvantages: Costly Improvements:  For already manufactured components, improving reliability necessitates root cause analysis and potentially expensive research. Limited Control:  If using Commercial Off-The-Shelf (COTS) components, integrators have minimal influence over design and reliability. Higher Costs:  More reliable components often come at a premium price. BQR Solution for Increasing Reliability: BQR’s fiXtress®  and CircuitHawk™  tools identify electronic circuit design errors during development, significantly lowering the risk of field failures while reducing overall development time. Additionally, fiXtress includes MTBF calculations according to leading standards, and professional analysis services are available, allowing you to focus on your core technology while leveraging BQR’s expertise. Method 2: Add Redundancy Advantages: Increased System Resilience:  Implementing redundancy decreases the system failure rate by requiring multiple failures for a system to fail. Common types of redundancy include: Hot Redundancy:  A redundant unit operates continuously, taking over immediately upon primary unit failure. Standby Redundancy:  A backup unit remains inactive until needed, which may result in downtime during the transition. Load Sharing:  Multiple units share the operational load. If one unit fails, the others compensate, though this may increase their failure rates. Disadvantages: Higher Costs:  More components lead to increased product and system costs. Maintenance Needs:  More active components can lower MTBF, resulting in a higher maintenance burden. Common Cause Failures:  If redundant components are identical, they may fail simultaneously due to shared vulnerabilities. Complexity:  A failure detection mechanism is often needed to switch to redundant components, introducing additional points of potential failure. BQR Solution for Redundancy and Safety Analysis: BQR’s RBD  software provides reliability allocation and calculation analyses, helping determine the best redundancy strategy during early design stages. Later, detailed calculations ensure the design meets reliability requirements. BQR’s Failure Mode and Effects Analysis (FMEA/FMECA)  and Fault Tree Analysis (FTA)  help assess the impacts and severity of various failure modes. These analyses are also available as professional services. Method 3: Failure Detection and Mitigation Advantages: Reduced Severity:  Failure detection systems and fail-safe mechanisms mitigate the impact of failures, leading to safer outcomes. Implementation Ease:  Detection systems can often be easier to implement than methods 1 and 2. Disadvantages: Operational Impact:  The operation of the product or system may be affected during a failure event. BQR Solution for Failure Detection: BQR’s unique testability analysis software  enables the development of optimal Built-In Test (BIT) policies to achieve high coverage of potential failures. Testability Analysis is also available as a professional service. Conclusion Achieving safety involves a strategic combination of the three methods outlined above. The optimal approach varies by product or system. For example: Critical Equipment:  Extensive production control and testing are essential to ensure high reliability. Remote Systems:  Redundancies are commonly employed in systems located in hard-to-reach areas. Electronic Circuits:  Many circuits are designed with multiple BITs for power-up, continuous operation, and maintenance. For tailored safety solutions for your products, contact us today!

News Provided By BQR Reliability Engineering Ltd. August 27, 2025, 10:00 GMT Delivering cutting-edge RAMS solutions to ensure mission-critical systems excel from design to deployment. RISHON LEZION, ISRAEL, August 27, 2025 / EINPresswire.com / -- BQR, a global leader in RAMS (Reliability, Availability, Maintainability, and Safety) Engineering and electronic design analyses automation, is proud to announce it has been awarded a significant contract by a leading European aerospace company. This landmark agreement marks a major milestone in BQR’s mission to deploy its patented reliability software and deliver world-class design and reliability solutions to the aerospace and defense industries. Renowned for their uncompromising standards and mission-critical systems for space, the aerospace and defense sectors demand exceptional precision, performance, and dependability. The organization defined a new, ultra-rigorous internal standard for electronic board durability, including compliance with an unprecedented 111 derating parameters. BQR has successfully delivered outstanding solutions, that empower engineering teams to perform early design analysis, automated design verification, derating evaluation, and MTBF prediction. These capabilities enable the development of robust, high-reliability systems-from schematic design through to deployment-meeting the most stringent industry requirements with unmatched precision. The technology behind BQR’s tools is built upon five proprietary patents, forming the foundational framework for next-generation reliability in aerospace systems. This follows BQR's Shift Left Methodology for RAMS Analysis™. “Being selected by a premier organization in the aerospace sector is both an honor and a powerful endorsement of our technology,” said Mr. Yizhak Bot, CEO of BQR. “This collaboration reflects the immense trust placed in our reliability-driven approach and the quality of our solutions. It reinforces our role as a key enabler in designing the next generation of high-performance, mission-critical systems.” This award further solidifies BQR’s position as a trusted partner to innovators in aerospace and defense and underscores the growing demand for next-generation Reliability Engineering tools that empower teams to reduce risk, accelerate time-to-market, and achieve uncompromised system integrity. Read The Original Press Release

SUMMARY & CONCLUSIONS By embracing a shift-left verification methodology, engineers can significantly enhance the reliability and robustness of critical electronic systems from the very start of development. The approach detailed in this paper – combining automated schematic rule checking, component derating analysis, and pre-layout stress simulation – essentially brings the rigor of later-stage testing and review into the schematic design phase. In addition, this approach identifies design flaws that could compromise mission success or safety at an early stage, permitting corrections at the schematic level rather than necessitating expensive hardware modifications. The methodology is grounded in proven best practices: it implements standard-based derating requirements, echoes the FMEA imperative of early failure mode elimination, and utilizes patented techniques for schematic and circuit verification. The expanded workflow increases the effort spent in early verification, but this investment pays off by reducing downstream problems many times over. In an era where systems are increasingly complex and failure intolerant, methods like these are becoming indispensable. As an evolving best practice, we foresee that shift-left verification flows will be integrated into standard electronic design toolchains, much as automated testing is now integral to software development.  1 INTRODUCTION In the development of critical electronic systems (such as aerospace, medical, or automotive devices), undetected design flaws can have disastrous consequences. A single schematic error—such as the absence of a pull-up resistor or an incorrect component connection—can result in a non-functional prototype, expensive PCB re-spins, or even field failures necessitating product recalls. Traditional workflows often postpone comprehensive verification until late in the design or testing phase, when fixes are difficult and expensive. Modern design-for-reliability practices instead emphasize shifting left – performing rigorous verification as early as possible, at the schematic stage, to catch issues before they propagate to hardware. As noted in industry guidance, integrating reliability checks early in the design process contrasts with older approaches that left such checks to later stages. This shift-left mindset is driven by a simple cost-benefit truth: the earlier a bug is found, the cheaper and easier it is to fix. Catching problems during the design phase can prevent enormous costs and safety risks down the line, especially for critical systems where a late-discovered flaw might necessitate scrapping or retrofitting all produced units. To implement the shift-left paradigm for critical electronic hardware, we propose a methodology that enables early verification of reliability and robustness directly on the circuit schematic. This approach performs comprehensive automated checks and simulations before PCB layout and prototyping. It combines three key elements: (1) logical schematic verification to ensure correct connectivity and design rule compliance, component derating analysis to check that parts operate within stress limits per reliability standards [Ref. 1], and (3) deep stress simulation to evaluate component stresses and margins under worst-case conditions. By integrating these steps into the early design stage, the methodology aims to identify design issues, component weaknesses, or rule violations that could lead to failures, thereby enabling designers to fix them long before physical implementation. This paper expands on each of these elements and describes the overall verification flow. It presents a structured “shift-left” verification process tailored for high-reliability electronics, with the goal of enhancing the depth of analysis performed in the schematic phase. We also highlight how this approach aligns with recognized industry best practices in reliability engineering (RAMS), such as early FMEA and derating guidelines, and reference relevant standards supporting the method. 2 BACKGROUND AND MOTIVATION Ensuring the reliability of critical electronics has historically involved extensive testing and analysis after a design was built – for instance, environmental stress testing of prototypes or formal failure mode analyses late in development. However, waiting until hardware testing or integration to uncover design flaws can be risky and inefficient. If a flaw originates in the circuit design itself (as opposed to a manufacturing defect), discovering it only after fabrication may require costly redesign and replacement of units in the field. In worst-case scenarios, an undetected design bug in a safety-critical system can lead to mission failure or endanger lives. Modern reliability engineering advocates for proactive measures early in the design lifecycle. Practices such as Design for Reliability (DfR) and Failure Modes and Effects Analysis (FMEA) stress early identification and mitigation of potential failure causes. The U.S. Department of Defense RAM Guide [Ref. 2], for example, notes that “the primary benefit of the FMEA is the early identification of all critical and catastrophic failure modes so they can be eliminated or minimized through design early in development.”. In other words, finding and fixing issues at the schematic or conceptual stage is far preferable to detecting them during testing or operation. This philosophy of early verification is encapsulated in the “shift-left” concept, which has gained traction not only in software testing but also in hardware design. By moving verification tasks (like design rule checking, stress analysis, etc.) to earlier phases, engineers can iterate quickly and address problems when changes are easier to implement. In the context of electronic hardware, a shift-left approach means performing pre-layout and pre-manufacturing analyses to validate that the design will meet reliability requirements. This involves using advanced Computer-Aided Engineering tools at the schematic capture stage itself, rather than after PCB layout. Early schematic reviews have been shown to catch many errors that would otherwise surface during board bring-up or environmental testing.  Additionally, by integrating reliability checks into the schematic design environment, design teams can get immediate feedback on issues like component stress or rule violations and correct them in real-time, thus significantly shortening the design cycle for high-reliability products. One industry report [Ref. 3] noted that employing automated reliability verification early can “Eliminating critical reliability errors early in the design flow can minimize complex, time-consuming verification iterations later on”. This not only improves confidence in the design’s robustness but also helps meet tight development schedules for complex systems. RAMS best practices further motivate this methodology. Standards and guides for high-reliability sectors (space, military, etc.) uniformly recommend derating components and analyzing stress under worst-case conditions during design as a means to enhance product reliability. For instance, NASA and ESA guidelines mandate derating of electronic components – i.e. using them at a fraction of their maximum ratings – to reduce the likelihood of overstress failures. The ECSS (European Cooperation for Space Standardization) specifically codifies derating requirements for nearly all EEE (electrical, electronic, and electromechanical) parts in standard ECSS-Q-ST-30-11C [Ref. 1], which must be adhered to in space hardware design. Compliance with such standards early in design avoids costly redesign if a non-compliant part is discovered later. Likewise, performing a form of stress simulation or worst-case circuit analysis during schematic design can reveal if a circuit is operating too close to the edge of its component capabilities (voltage, current, power, thermal limits, etc.), and allow redesign or component changes before any PCB is built. This approach mirrors the intent of reliability prediction models (like MIL-HDBK-217 [Ref. 4] or FIDES [Ref. 5]) which attempt to estimate failure rates based on stress – but here we integrate the prediction directly by actually calculating stress in the circuit under simulated conditions. In summary, the motivation for a shift-left verification flow is to embed reliability assurance into the early design steps, ensuring that by the time the design is ready for layout and manufacturing, it has already been vetted for logical correctness, component robustness, and compliance with reliability criteria. 3 OVERVIEW OF THE SHIFT-LEFT VERIFICATION FLOW The following figure presents a suggested “Shift Left” flow for design of critical electronics:   ​ ​ Figure 1 – “Shift Left” flow for design of critical electronics ​ The high-level steps shown in the figure are: design the circuit function by function. For each function, the engineer conducts logical schematic verification to ensure that the components are connected correctly and not missing e.g. decoupling capacitors. Next, the engineer conducts component derating analysis to verify that the components will withstand the applied stresses. After the circuit functions have been designed and verified, a deeper analysis is conducted by stress simulation. The calculated stresses help identify additional design.The proposed verification flow consists of two complementary tool-driven stages applied during schematic design, prior to PCB layout: (A) Automated Schematic Review with Derating Compliance and (B) Pre-Layout Parametric Stress Simulation. Each stage is supported by a specialized software tool (proprietary or commercial), and together they implement a comprehensive early verification per the shift-left methodology. The process can be summarized as follows:  Stage A: ECAD-Integrated Rule-Based Schematic Verification and Derating Checks. In this stage, the schematic is analyzed against a set of design rules and reliability guidelines. The tool parses the schematic netlist and components, then applies a library of rules that encode both logical design constraints and derating requirements. This includes checking for correct connectivity, absence of common schematic errors, presence of required safety components, and ensuring that each component’s applied stress (voltage, current, power, etc.) does not exceed derated limits as defined by standard. The output is a report of any rule violations or warnings for the designer to address.Note: During this step the design engineer inputs the operational stresses for component derating analysis based on his understanding of the expected circuit behavior.   Stage B: Pre-Layout Parametric Stress and Reliability Simulation. When the circuit is complete, a more in-depth analysis can be performed by simulating the circuit’s behavior under various worst-case scenarios and design parameter extremes. Using the schematic and part models, the tool calculates the electrical values (node potentials, branch currents, power dissipation in components, etc.) across the circuit. By sweeping through corner-case conditions (such as maximum input voltage, lowest temperature, highest load, component tolerances, etc.), the tool evaluates whether components remain within safe operating limits with adequate margins. It may also calculate reliability metrics like estimated component failure rates or Mean Time Between Failures (MTBF) based on the stress results. This stage effectively serves as a “virtual stress test” of the design in the computer, before any physical prototype is built. In addition to detailed stress analysis the tool identifies design errors that may otherwise be very hard to identify (see examples in next sections). These two stages are implemented with two distinct tools working in tandem. Tool A is typically a plugin or module integrated into the ECAD (Electronic CAD) schematic capture environment. It operates as an Automated Schematic Review (ASR) system, continuously or on-demand checking the design against rule sets. Tool B is a simulation engine (which could be integrated or standalone) that takes the schematic netlist and performs advanced analyses (electrical simulation, network solving, worst-case analysis) to predict performance and stress outcomes. The combined workflow allows an engineer to alternate between schematic entry and verification seamlessly: after drawing the circuit, they run Tool A to catch any rule violations and adjust the design, then run Tool B to see if the design can withstand extremes and adjust as needed. This iterative process continues until the schematic satisfies all verification criteria, thereby providing assurance of the design’s robustness prior to hardware. In the following sections, we delve deeper into each stage of this methodology. 4 INCREMENTAL ECAD-INTEGRATED VERIFICATION ​This tool assists the electronics engineer in doing a self function by function verification for the circuit. The tool provides two types of analyses: 4.1    Logical Schematic Review The logical schematic review is based on a set of “common rules” as well as user customizable rules. The common rules include tests for identifying floating pins, floating IC ground nets, conflicts between inputs and outputs, missing decoupling capacitors and more.The custom rules engine lets the user define rules for connectivity between object1 and object2 via a connecting element. This flexible rules engine can be customized for each company according to their design policies e.g. naming conventions for net names.A potential issue for such heuristic based rules is the occurrence of false warnings that take valuable time to review and dismiss. This issue is minimized by fine-tuning the custom rules as well as by providing the user with filtering options for the warnings. 4.2    Component Derating Analysis Many engineers use rules of thumb during circuit design for derating, e.g. select a capacitor where the expected operational voltage is 50% from the capacitor datasheet volage rating. However, this is not enough for critical electronics that may experience high temperatures. The suggested tool accounts for derating curves which are defined per component type according to company policy or derating standard. Component rated values are kept in a library, and the tool provides methods to minimize the engineer’s work in defining the operational stresses. Once derating curves are defined, component ratings exist in the library, board temperature is defined and operation stresses are set, the derating analysis is done for the selected circuit function. 4.3    Benefits Using such a tool provides several benefits: Identifying design errors early in the design prevents costly design cycles and reworks. Custom verification rules can be reused for verification of the next projects. Operational stresses are saved as component parameters in the schematic for future reuse and for additional analyses such as MTBF prediction.  Keeping the data in the schematic increases analysis traceability. When the circuit design is complete, before layout, a parametric stress simulation can be done:  5 DEEP STRESS ANALYSIS ​ 5.1    Stress Simulation The second tool is based on calculation of the component stresses such as power, voltage and current for each component. This is in contrast to the previous steps where the engineer inputted the stresses according to his understanding. Unlike a full SPICE simulation that might require detailed models and significant manual setup, this tool is oriented toward early design when not all details are fixed. It may use simplified models that allow analysis over very large circuits.This tool can identify a host of design errors that are otherwise very hard to detect.  5.2    Operation Principle The stress calculation is achieved by the following steps: Get BOM and NetList from the ECAD. Define circuit inputs and output loads. Define IC pin types and internal functions. Define component electrical parameters in a components library. Define state vectors where each vector entry represents the state of a nonlinear component, e.g. transistor state. For each states vector solve the linear circuit equations to obtain current, potential and power everywhere. When the stress calculation is complete, parametric schematic verification is done, comparing the calculated values to component voltage specs, and conducting pin level derating analysis.  6 EXAMPLES ​The tools for implementing the shift left flow have been created and used for verification of circuit designs regarding leading mission critical electronics providers. Following are examples of design issues which were identified using the suggested flow and tools: Schematic review of a circuit function revealed that I2C communication lines were accidently switched. This was identified due to violation of the following connectivity rule: pin name that includes the string “SCL” should be connected to a net name that includes the same string “SCL”. Instead, it was found that pin “SCL” was connected to net “SDA”.This would have prevented I2C communication from operating properly.  The schematic review also identified floating ground as violation of another rule: Pin name that includes the string “GND” must be connected to ground.  During component derating analysis of a function, a derating issue was identified regarding capacitor C74. The following screenshot presents this case:    ​ ​ ​ Figure 2 – Component Derating Analysis ​ The capacitor rated voltage is 6.3V, the applied operational stress is 5V, the derating factor was found to be 60% at 25oC, therefore the operational stress should not exceed 3.78V. The tool provided a recommendation to replace C74 with a capacitor that has a voltage rating above 8.3V. The design engineer followed the recommendation and solved the issue. Derating analysis also identified a case of over design in a space product, where the designer selected components that are too big. It was found that 3 capacitors could be replaced with smaller parts that have a lower rating, saving valuable space in the circuit while adhering to the derating requirements. Verification based on stress simulation identified the following issue: Digital pin in IC should have a voltage that denotes ‘0’ or ‘1’, however the calculated voltage was found to be an illegal value which is between ‘0’ and ‘1’. The allowed voltage ranges for IC digital input pins were defined in the IC pin library, and compared to calculated input voltage by the simulation. The source of the error was accidental switching of voltage divider resistors.This issue could have caused erratic circuit behavior.  Another issue that was identified during the simulation-based verification was: Low voltage supply for IC. The IC power input voltage and current consumption were defined in the IC pin library, and compared to simulated value.The source of the issue was selection of a resistor with high resistance between the IC pin and voltage regulator. After the circuit simulation, potentials are known for each circuit node and currents are known through each pin. Then pin level component derating (also known as part stress analysis) can be done. During this verification stage overcurrent was identified in the power pins of a connector. This would have shortened the product life.  7 STATE OF THE ART Following is a comparison of the above-mentioned tools to common practices and popular tools: Logical schematic review exists in many ECAD tools (known as ERC or DRC). However, these tools do not offer the level of rule customization which is described in this paper. Component derating analysis is often conducted in one of two ways: rough assessment e.g. 50% derating assumption, or by using cumbersome excel sheets. The component derating suggested in this paper accounts for the detailed temperature derating curve for each component type to comply with standards such as ECSS-Q-ST-30-11C. While circuit simulation tools such as SPICE provide detailed time domain information regarding the circuit behavior, the simulation requires many input parameters for each component, may experience convergence issues, and is limited to small circuits. SPICE is very useful for timing analysis but is not a viable solution for stress analysis in large circuits. The stress simulation tool that is suggested in this paper provides a balance between achieved accuracy and calculation effort, supporting very large circuits. Online tools also exist where the engineer submits his design for analysis and receives a report. This has the potential of timesaving for the engineer. However, there are two potential issues with this method: 1. Data security. 2. The analysis is done remotely, and the engineer has no control over it. If the input data is incorrect or incomplete, the submit process has to be repeated. The ECAD integrated tool suggested in this paper solves these issues: data is kept locally and analysis reruns and corrections can be done in real-time.  8 CONCLUSIONS AND FUTURE WORK A verification flow was introduced for implementing a shift left methodology in circuit verification as well as software tools for each verification step. Details were provided regarding the tools operation principles and actual examples were provided regarding circuit design errors that were identified by mission critical electronics developers using this methodology. Recent advancements in artificial intelligence and large language models present new opportunities to further automate circuit-verification processes. We plan to study the benefits and potential risks of using AI for such tasks.  REFERENCES ​ ECSS Secretariat, Space Product Assurance – Derating – EEE Components, ECSS-Q-ST-30-11C, Rev.2, 2021 DOD GUIDE FOR ACHIEVING RELIABILITY, AVAILABILITY, AND MAINTAINABILITY , 20095 Siemens, How can I run reliability checks early in the design cycle? U.S. Department of Defense, MIL-HDBK-217F Notice 2: Reliability Prediction of Electronic Equipment, 1995 FIDES Group, FIDES Guide 2022 Edition A: Reliability Methodology for Electronic Systems, 2022 ​ ACKNOWLEDGEMENTS We would like to thank ChatGPT for providing helpful authoring tips for this paper.  Contact Us to Learn More​

News Provided By BQR August 6, 2025, 10:00 GMT BQR Reliability Engineering Ltd., a global leader in Reliability, Availability, Maintainability, and Safety (RAMS) software and services, is proud to celebrate 35 years of pioneering excellence in mission-critical electronics verification. During the anniversary celebration, company Founder and CEO Mr. Yizhak Bot shared a compelling case study that exemplifies the critical importance of comprehensive electronics verification in high-stakes aerospace missions. Several years ago, BQR was contacted by a satellite manufacturer facing a critical situation: their $100 million satellite had failed 4.5 years after launch, with an identical second satellite scheduled for launch within six months. The manufacturer's internal teams were unable to identify the root cause of the failure, putting the second $100 million investment at severe risk. "The company contacted BQR because they were unable to identify the root cause of the failure," explained Mr. Bot. "Using our Circuit-Hawk software, BQR engineers simulated the satellite electronics at various operational states and identified that in a specific operation state, a specific component was over-stressed to the point that it might burn." Initially, the satellite manufacturer's representatives were skeptical that such a seemingly minor component issue could cause total satellite failure. However, Mr. Bot proposed a decisive test:"I asked them to test this issue in the lab on the second satellite, which was still on the ground. They did it and indeed the component burnt." Prevention Through Advanced Simulation: The ground-based testing validated BQR's simulation results, enabling the manufacturer to quickly implement a design fix and successfully launch the second satellite, preventing it from suffering the same fate as its predecessor. The intervention saved the full $100 million value of the second satellite. "If they were using BQR simulation at the beginning, they could have also saved the first satellite and prevented another $100 million loss," Mr. Bot noted. "This demonstrates the importance of doing detailed part stress analysis and circuit design analysis using the best available tools." 𝗔𝗯𝗼𝘂𝘁 𝗕𝗤𝗥 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 BQR is a global leader in reliability engineering and electronic design automation, empowering engineers to create robust, reliable, and optimized electronic systems. With decades of experience supporting giants across aerospace, defense, automotive, energy, medical, telecom, and high-performance industries, BQR delivers software tools and services that span the full lifecycle of electronics - from initial schematic to field maintenance. The result: reduced design time, minimized costly rework, and greater confidence in mission-critical systems. BQR’s solutions focus on early design reliability analysis, which is the new "Shift-Left Methodology for RAMS Analysis™ " automated design analyses & components derating, and MTBF prediction - enabling engineers to identify hidden risks, optimize component selection, and ensure product reliability from day one. Read The Original Press Release

News Provided By BQR October 03, 2024, 15:06 GMT BQR Reliability Engineering BQR's fiXtress® Software Automates Reliability Analysis for Multi-Board Design and is Now Compliant with the Latest Aerospace Standard, FIDES 22. ISRAEL, October 3, 2024 / EINPresswire.com/ -- BQR Reliability Engineering Ltd, a leading provider of reliability engineering software and services, is pleased to announce that its flagship product, fiXtress®, has achieved full compliance with the FIDES 22 standard. This milestone highlights BQR’s ongoing commitment to delivering cutting-edge solutions that meet the evolving requirements of the aerospace electronics industry. FIDES 22, the most recent update to the reliability prediction standard developed by a consortium of European aerospace and defense companies, introduces several enhancements over its predecessor, FIDES 2009. Some of the key updates include: • 𝗠𝗼𝗿𝗲 𝗥𝗲𝗮𝗹𝗶𝘀𝘁𝗶𝗰 𝗙𝗮𝗶𝗹𝘂𝗿𝗲 𝗥𝗮𝘁𝗲 𝗩𝗮𝗹𝘂𝗲𝘀 𝗳𝗼𝗿 𝗠𝗼𝗱𝗲𝗿𝗻 𝗖𝗼𝗺𝗽𝗼𝗻𝗲𝗻𝘁𝘀: Enhances the accuracy of reliability predictions. • 𝗡𝗲𝘄 𝗣𝗮𝗰𝗸𝗮𝗴𝗲 𝗖𝗮𝘁𝗲𝗴𝗼𝗿𝗶𝗲𝘀 𝗳𝗼𝗿 𝗜𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗲𝗱 𝗖𝗶𝗿𝗰𝘂𝗶𝘁𝘀: Provides improved classification for contemporary chip designs. • 𝗠𝗼𝗱𝗲𝗹 𝗳𝗼𝗿 𝗣𝗹𝗮𝘀𝘁𝗶𝗰 𝗙𝗶𝗹𝗺 𝗖𝗮𝗽𝗮𝗰𝗶𝘁𝗼𝗿𝘀: Delivers dedicated analysis capabilities for this prevalent component. By aligning with the FIDES 22 standard, fiXtress® equips engineers with a powerful tool for predicting product lifespan, identifying potential failure points, and optimizing designs for maximum reliability and safety. The software is particularly beneficial for industries such as aerospace, defense, automotive, and energy, where product reliability is critical. “We are thrilled to announce fiXtress®’s compliance with the FIDES 22 standard,” said Yizhak Bot, Founder and CEO of BQR Reliability Engineering. “This accomplishment underscores our dedication to providing state-of-the-art solutions that enable engineers to design and develop highly reliable products. By integrating FIDES 22 into fiXtress®, we empower our customers to make well-informed decisions, mitigate risks, and achieve greater success.” fiXtress® is renowned for its comprehensive reliability analysis capabilities, including electrical stress and derating analysis, thermal management, MTBF prediction, and EOS (Electrical OverStress) violation detection. With the addition of FIDES 22 compliance, the software now offers an even more robust and comprehensive solution for ensuring product reliability. 𝗔𝗯𝗼𝘂𝘁 𝗕𝗤𝗥 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 BQR Reliability Engineering is a global leader in providing reliability engineering software and services. With a proven track record of excellence, BQR empowers organizations to enhance product reliability, reduce costs, and accelerate time-to-market. Emphasizing a "shift-left" philosophy, BQR advocates for early analysis in the design phase to minimize development time, optimize resource allocation, and reduce costs. BQR's software revolutionizes RAMS analysis with unparalleled accuracy and ease of use. Their extensive portfolio includes a range of reliability software solutions, prominently featuring the ECAD Plugin. This innovative tool seamlessly bridges the gap between PCB design and reliability analysis, ensuring dynamic linking and real-time synchronization of design changes with analysis results. The ECAD Plugin enhances accuracy by linking analyses directly to the latest schematic version and incorporating actual electrical and thermal data, making component failure rates more realistic for other RAMS analyses. This advanced approach eliminates the inaccuracies common in traditional methods like Excel formulas, providing instant, reliable insights. As a result, BQR's software streamlines verification and validation processes, significantly enhancing the safety and reliability of products in mission-critical sectors such as aerospace, automotive, defense, and medical devices. For more information, visit our website . Read the Original Press Release

News Provided By BQR July 23, 2025, 20:00 GMT BQR Reliability Engineering Ltd., an industry leader in electronic reliability solutions, announces its participation at the first European RAMS (Reliability, Availability, Maintainability, and Safety) Symposium, held in Amsterdam in August 2025. Mr. Yizhak Bot, Founder and CEO of BQR and Dr. Amir Segal, Engineering Manager, will present a pioneering paper introducing the revolutionary Shift-Left Methodology in RAMS Analysis ™ for critical electronics. This marks the first time the "Shift-Left" Methodology, typically associated with electronics development, is formally applied to RAMS analyses. Unlike conventional methods that rely on physical testing after production or upon completion of the entire design process, BQR's Shift-Left methodology leverages automated schematic rule checking, component derating analysis, and pre-layout stress simulations at the schematic phase of electronic product design. "Implementing "Shift-Left Methodology for RAMS analysis" ™ significantly enhances product reliability and robustness," says Yizhak Bot, CEO and founder of BQR. "Much like a spell checker in test editing, BQR tools, such as Synthelyzer, immediately detect design errors and potential faults as soon as the designer drafts the schematic, thus preventing costly and time-consuming late-stage modifications." By adopting BQR’s innovative Shift-Left approach, manufacturers can deliver more reliable and robust products faster and more economically, substantially reducing design cycles, development costs, and improving product safety and performance. Join Mr. Yizhak Bot and Dr. Amir Segal at the European RAMS Symposium to explore how the integration of advanced BQR solutions can revolutionize the reliability and safety standards for critical electronic systems across industries. 𝗔𝗯𝗼𝘂𝘁 𝗕𝗤𝗥 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 BQR Reliability Engineering Ltd. is a global pioneer in reliability engineering solutions, dedicated to providing sophisticated software and methodologies that empower designers to create robust, reliable, and efficient electronic and mechanical products. With decades of expertise and innovation, BQR continues to set industry benchmarks for reliability and product lifecycle excellence. Read The Original Press Release

News Provided By BQR September 26, 2024, 15:06 GMT Share This Article BQR Reliability Engineering BQR's Synthelyzer™ plugin automates electrical stress derating and MTBF prediction, enhancing design efficiency and component reliability for engineers. ISRAEL, September 26, 2024 / EINPresswire.com/ -- BQR Reliability Engineering Ltd., a leader in reliability engineering software and services, today announced the launch of Synthelyzer™, a groundbreaking ECAD plugin designed to streamline electrical stress derating and MTBF (Mean Time Between Failures) prediction processes for electronic design engineers. Synthelyzer™ integrates seamlessly with popular ECAD tools, offering engineers a powerful solution for accurately assessing component reliability and optimizing designs for long-term performance. By automating complex calculations and providing real-time feedback, Synthelyzer™ significantly reduces design cycles and enhances product reliability. 𝗞𝗲𝘆 𝗙𝗲𝗮𝘁𝘂𝗿𝗲𝘀 𝗼𝗳 𝗦𝘆𝗻𝘁𝗵𝗲𝗹𝘆𝘇𝗲𝗿𝗧𝗠: • 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗲𝗱 𝗦𝘁𝗿𝗲𝘀𝘀 𝗗𝗲𝗿𝗮𝘁𝗶𝗻𝗴: Automatically calculates electronic component stress based on electrical and thermal parameters, ensuring compliance with   industry derating standards. • 𝗔𝗰𝗰𝘂𝗿𝗮𝘁𝗲 𝗠𝗧𝗕𝗙 𝗣𝗿𝗲𝗱𝗶𝗰𝘁𝗶𝗼𝗻: Utilizes advanced algorithms to predict MTBF for electronic assemblies precisely, enabling informed design decisions and   maintenance forecasting. •𝗦𝗲𝗮𝗺𝗹𝗲𝘀𝘀 𝗘𝗖𝗔𝗗 𝗜𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗶𝗼𝗻: Integrates with leading ECAD tools, streamlining workflows and eliminating manual data entry during electronic schematic design. • 𝗥𝗲𝗮𝗹-𝘁𝗶𝗺𝗲 𝗙𝗲𝗲𝗱𝗯𝗮𝗰𝗸: Provides instant feedback on design and recommends design changes, allowing engineers to identify and address potential reliability   issues and optimize component rating early in the development process. • 𝗖𝗼𝗺𝗽𝗿𝗲𝗵𝗲𝗻𝘀𝗶𝘃𝗲 𝗥𝗲𝗽𝗼𝗿𝘁𝗶𝗻𝗴: Generates detailed reports on stress derating, MTBF calculations, and other key reliability metrics, facilitating compliance with   industry standards and regulatory requirements. 𝗜𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗶𝗼𝗻 𝘄𝗶𝘁𝗵 𝗕𝗤𝗥'𝘀 𝗦𝗼𝗹𝘂𝘁𝗶𝗼𝗻𝘀: • 𝗕𝗤𝗥'𝘀 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗲𝗱 𝗦𝗼𝗳𝘁𝘄𝗮𝗿𝗲 𝗳𝗼𝗿 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗔𝗻𝗮𝗹𝘆𝘀𝗶𝘀 𝗳𝗼𝗿 𝗠𝘂𝗹𝘁𝗶-𝗕𝗼𝗮𝗿𝗱 𝗗𝗲𝘀𝗶𝗴𝗻: SynthelyzerTM integrates with BQR's automated software for reliability analysis in multi-  board designs, offering advanced capabilities for electrical stress analysis, thermal management, and EOS (Electrical OverStress) violation detection. This   integration provides a robust solution for optimizing product reliability across complex multi-board systems. •𝗕𝗤𝗥'𝘀 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗲𝗱 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆, 𝗔𝘃𝗮𝗶𝗹𝗮𝗯𝗶𝗹𝗶𝘁𝘆, 𝗠𝗮𝗶𝗻𝘁𝗮𝗶𝗻𝗮𝗯𝗶𝗹𝗶𝘁𝘆, 𝗮𝗻𝗱 𝗦𝗮𝗳𝗲𝘁𝘆 (𝗥𝗔𝗠𝗦) 𝗔𝗻𝗮𝗹𝘆𝘀𝗶𝘀 𝗳𝗼𝗿 𝗘𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰 𝗦𝘆𝘀𝘁𝗲𝗺𝘀: SynthelyzerTM also integrates with BQR's RAMS analysis tool, delivering comprehensive functionalities for reliability prediction, availability assessment, maintainability analysis, and safety analysis. This ensures a   thorough evaluation of electronic system performance and resilience. 𝗦𝗵𝗶𝗳𝘁-𝗟𝗲𝗳𝘁 𝗔𝗽𝗽𝗿𝗼𝗮𝗰𝗵: With Synthelyzer™, engineers can proactively address reliability concerns early in the design cycle, adopting a "shift-left" approach. Its seamless ECAD integration and real-time feedback empower designers to identify and mitigate potential issues, ultimately reducing development time and costs. As Yizhak Bot, founder and CEO of BQR Reliability Engineering, stated, "Synthelyzer™ is a game-changer, automating time-consuming tasks and providing precise insights to enable the design of more reliable and robust electronic products." Synthelyzer™ is now available for integration with popular ECAD tools such as Altium Designer, Cadence-OrCAD, and Siemens-EDA. For more information or to request a demo, please visit our website . 𝗔𝗯𝗼𝘂𝘁 𝗕𝗤𝗥 𝗥𝗲𝗹𝗶𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 BQR Reliability Engineering is a global leader in providing innovative software solutions and services for reliability engineering in the electronic industry. We focus on improving product quality, reducing costs, and accelerating time-to-market, helping organizations achieve their reliability goals. Read the Original Press Release

Introduction In the fast-paced world of PCB design, incremental design review has emerged as a critical practice to enhance quality and reduce rework. However, as designs become more complex, manual review processes often struggle to keep pace. This is where tool-assisted incremental design review comes into play. By automating critical verification tasks, tools like BQR’s Synthelyzer™ empower engineers to catch errors early, focus on incremental improvements, and accelerate time-to-market. What is an Incremental Design Review? An incremental design review continuously verifies a PCB design at each stage of its development. Rather than waiting until the final design stage to perform an exhaustive review, engineers assess their work in smaller, manageable increments. This proactive approach has several key benefits: Early Error Detection: Identifying issues early in the design cycle prevents costly rework and reduces the risk of downstream failures. Focused Improvement: Incremental reviews allow engineers to address specific areas of concern without being overwhelmed by the entire design’s complexity. Faster Iterations: Smaller, incremental changes are easier to verify, speeding up the design process. The Role of Tools in Incremental Design Review While the incremental approach is practical, its success depends on the ability to perform rapid and accurate reviews. Manual processes often fall short, as they are time-consuming and prone to human error. Tool-assisted review bridges this gap, offering automated insights and ensuring comprehensive verification at every step. Key Advantages of Tool-Assisted Incremental Review: Automated, Comprehensive Analysis: Unlike manual reviews, tools like Synthelyzer™ enable electrical stress analysis of each component. Analysis includes connectivity and component-level derating analysis ensuring that incremental design changes do not introduce new errors or compromise reliability. Data-Driven Insights: Tools generate detailed reports with actionable recommendations, helping engineers make informed decisions during each review cycle. Faster Turnaround: Automation significantly reduces the time required for each review, enabling engineers to iterate faster and bring products to market more efficiently. How Tool-Assisted Incremental Design Review Works Stage 1: Pre-Layout Verification At the initial design stages, Synthelyzer™ integrates directly with ECAD platforms to evaluate schematic integrity and perform component stress analysis. This includes checks for: ● Voltage and current mismatches ● Component derating compliance ● Grounding issues By addressing these issues early, engineers can avoid rework during the layout stage. Stage 2: Layout Optimization To verify the schematic design right before the layout phase, CircuitHawk™ analyzes signal path with advanced ERC and electrical stress simulation. Pin-level detailed analysis ensures that there are no overstresses or voltage mismatches, for example: ensuring that digital signals have voltage states according to spec. Stage 3: System-Level Analysis As the design progresses, fiXtress® provides system-level, comprehensive reliability assessments to detect components with low reliability and identify critical overstressed parts. This includes: ● Multi-board analysis for complex systems ● Mean Time Between Failures (MTBF) predictions ● Electrical overstress (EOS) violation detection ● Overdesign Risks , for example, using capacitors with unnecessarily large footprints wastes board space and adds weight, which is especially critical for satellites and small enclosures where size and weight optimization are essential. System-level insights allow engineers to address potential failures that may not be apparent at the component or board level. Why Incremental Design Review Matters Reduced Development Costs: Early error detection minimizes the need for expensive late-stage revisions and rework. Improved Design Quality: Engineers can ensure that the final design meets reliability and performance standards by verifying each incremental change. Accelerated Time-to-Market: Faster iterations enabled by tool-assisted review processes translate to shorter development cycles and a competitive edge. Enhanced Collaboration: Automated tools provide clear, data-driven insights that facilitate team members' collaboration, ensuring everyone is aligned with design objectives. A Small Step for the Engineer, A Giant Leap for Product Reliability: Function-by-function, easy changes accumulate to create a fully optimized and highly reliable product. BQR’s Solutions for Incremental Design Review Synthelyzer™ Synthelyzer™ is an intelligent ECAD plugin that automates component stress analysis and derating, ensuring optimal selection and reducing design errors. Seamlessly integrated into your workflow, it acts as a self-review assistant, proactively identifying potential issues to enhance PCB reliability and accelerate development. CircuitHawk™ CircuitHawk™ provides comprehensive schematic analysis, stress verification, and connectivity verification by simulation, enabling engineers to catch critical schematic logic errors before proceeding to the physical layout phase. fiXtress® FiXtress® offers system-level reliability analysis and MTBF predictions, ensuring that incremental changes align with overall system objectives. Smarter Reviews, Better Designs Tool-assisted incremental design review is transforming the way engineers approach PCB development. Design teams can achieve higher quality, faster iterations, and reduced costs by integrating automated verification tools into their workflows. Tools like Synthelyzer™, CircuitHawk™ and fiXtress® not only streamline the review process but empower engineers to focus on innovation and optimization. Ready to embrace the future of PCB design? Explore how BQR’s design review tools can help your team deliver exceptional results with every design iteration. Contact us today!